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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max8743 is a dual pulse-width modulation (pwm) controller configured for step-down (buck) topologies that provides the high efficiency, excellent transient response, and high dc output accuracy necessary for stepping down high-voltage batteries to generate low- voltage chipset and ram power supplies in notebook computers. the cs_ inputs can be used with low-side sense resistors to provide accurate current limits or can be connected to lx_, using low-side mosfets as cur- rent-sense elements. high output impedance in shut- down eliminates negative output voltages, saving the cost of a schottky diode at the output. the on-demand pwm controllers are free running, con- stant on-time with input feed-forward. this configuration provides ultra-fast transient response, wide input-output differential range, low supply current, and tight load-reg- ulation characteristics. the max8743 is simple and easy to compensate. single-stage buck conversion allows the max8743 to directly step down high-voltage batteries for the highest possible efficiency. alternatively, two-stage conversion (stepping down the 5v system supply instead of the bat- tery at a higher switching frequency) allows the minimum possible physical size. the max8743 is intended for generating chipset, dram, cpu i/o, or other low-voltage supplies down to 1v. the max8743 is available in 28-pin qsop and 36-pin thin qfn packages. applications notebook computers cpu core supplies chipset/ram supplies as low as 1v 1.8v and 2.5v i/o supplies features ? ultra-high efficiency ? accurate current-limit option ? quick-pwm with 100ns load-step response ? 1% v out accuracy over line and load ? high output impedance in shutdown ? dual mode fixed 1.8v/1.5v/adj or 2.5v/adj outputs ? adjustable 1v to 5.5v output range ? 2v to 28v battery input range ? 200khz/300khz/420khz/540khz nominal switching frequency ? adjustable overvoltage protection ? 1.7ms digital soft-start ? drives large synchronous-rectifier fets ? power-good window comparator ? 2v ?% reference output max8743 dual, high-efficiency, step-down controller with high impedance in shutdown ________________________________________________________________ maxim integrated products 1 19-3318; rev 0; 6/04 pin configurations appear at end of data sheet. quick-pwm and dual mode are trademarks of maxim integrated products, inc. v cc output1 1.8v battery 4.5v to 28v ilim1 on2 dl1 ton out1 lx1 dh1 fb1 gnd v dd bst1 ilim2 on1 ref dl2 cs2 out2 lx2 dh2 fb2 v+ bst2 skip 5v input pgood output2 2.5v max8743eei uvp ovp cs1 minimal operating circuit ordering information part temp range pin-package max8743eei -40? to +85? 28 qsop MAX8743ETX -40? to +85? 36 thin qfn 6mm x 6mm
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 2 _______________________________________________________________________________________ absolute maximum ratings (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to agnd..............................................................-0.3 to +30v v cc to agnd............................................................-0.3v to +6v v dd to pgnd............................................................-0.3v to +6v agnd to pgnd .....................................................-0.3v to +0.3v pgood, out_ to agnd..........................................-0.3v to +6v ovp, uvp, ilim_, fb_, ref, skip , ton, on_ to agnd......................-0.3v to (v cc + 0.3v) dl_ to pgnd ..............................................-0.3v to (v dd + 0.3v) bst_ to agnd........................................................-0.3v to +36v cs_ to agnd.............................................................-6v to +30v dh1 to lx1 ..............................................-0.3v to (v bst1 + 0.3v) lx_ to bst_ ..............................................................-6v to +0.3v dh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) ref short circuit to gnd ...........................................continuous continuous power dissipation (t a = +70?) 28-pin qsop (derate 10.8mw/? above +70?)........860mw 36-pin 6mm ? 6mm thin qfn (derate 26.3mw/? above +70?) .............................2105mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (circuit of figure 1, v dd = v cc = 5v, skip = agnd, v+ = 15v, t a = 0? to +85? , typical values are at +25?, unless otherwise noted.) parameter symbol conditions min typ max units pwm controllers v+ battery voltage, v+ 2 28 input voltage range v cc /v dd v cc , v dd 4.5 5.5 v fb1 to agnd 1.782 1.8 1.818 fb1 to v cc 1.485 1.5 1.515 v+ = 2v to 28v, i load = 0 to 8a, skip = v cc , +25? to +85? fb1 to out1 0.99 1 1.01 fb1 to agnd 1.773 1.8 1.827 fb1 to v cc 1.477 1.5 1.523 dc output voltage out1 (note 2) v out1 v+ = 2v to 28v, i load = 0 to 8a, skip = v cc , 0? to +85? fb1 to out1 0.985 1 1.015 v fb2 to agnd 2.475 2.5 2.525 v+ = 4.5v to 28v, i load = 0 to 4a, skip = v cc , +25? to +85? fb2 to out2 0.99 1 1.01 fb2 to agnd 2.463 2.5 2.537 dc output voltage out2 (note 2) v out2 v+ = 4.5v to 28v, i load = 0 to 4a, skip = v cc , 0? to +85? fb2 to out2 0.985 1 1.015 v output voltage adjust range out1, out2 1 5.5 v dual-mode threshold, low ovp, fb_ 0.05 0.1 0.15 v ovp, ilim_ v cc - 1.5 v cc - 0.4 dual-mode threshold, high fb1 1.9 2.0 2.1 v r out1 v out1 = 1.5v 75 out_ input resistance r out2 v out2 = 2.5v 100 k ? fb_ input-bias current i fb -0.1 +0.1 ? soft-start ramp time zero to full ilim 1700 ? note 1: for the max8743eei, agnd and pgnd refer to a single pin designated gnd.
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v dd = v cc = 5v, skip = agnd, v+ = 15v, t a = 0? to +85? , typical values are at +25?, unless otherwise noted.) parameter symbol conditions min typ max units ton = agnd 120 137 153 ton = ref 153 174 195 ton = float 222 247 272 on-time, side 1 t on1 v+ = 24v, v out1 = 2v (note 3) ton = v cc 316 353 390 ns ton = agnd 160 182 204 ton = ref 205 234 263 ton = float 301 336 371 on-time, side 2 t on2 v+ = 24v, v out2 = 2v (note 3) ton = v cc 432 483 534 ns ton = agnd 125 135 145 ton = ref 125 135 145 ton = float 125 135 145 on-time tracking on-time 2 with respect to on- time 1 (note 3) ton = v cc 125 135 145 % minimum off-time t off (note 3) 400 500 ns quiescent supply current (v cc )i cc fb_ forced above the regulation point 1100 1500 ? quiescent supply current (v dd )i dd fb_ forced above the regulation point <1 5 a quiescent supply current (v+) i+ measured at v+ 25 70 ? shutdown supply current (v cc ) on1 = on2 = agnd, ovp = v cc <1 5 a shutdown supply current (v dd ) on1 = on2 = agnd <1 5 a shutdown supply current (v+) on1 = on2 = agnd, measured at v+, v cc = agnd or 5v <1 5 a reference voltage v ref v cc = 4.5v to 5.5v, no external ref load 1.98 2 2.02 v reference load regulation i ref = 0 to 50? 0.01 v ref sink current ref in regulation 10 a ref fault lockout voltage falling edge, hysteresis = 40mv 1.6 v overvoltage trip threshold (fixed-threshold mode) ovp = agnd, with respect to error- comparator trip threshold 112 114 117 % 1v < v ovp < 1.8v, external feedback, measured at fb_ with respect to v ovp -28 0 +28 mv overvoltage comparator offset (adjustable-threshold mode) 1v < v ovp < 1.8v, internal feedback, measured at out_ with respect to out_ regulation point -3.5 0 +3.5 % ovp input leakage current 1v < v ovp < 1.8v -100 <1 +100 na overvoltage fault propagation delay fb_ forced 2% above trip threshold 1.5 ? output undervoltage threshold uvp = v cc , with respect to error-comparator trip threshold 65 70 75 % output undervoltage protection blanking time from on_ signal going high 10 30 ms
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v dd = v cc = 5v, skip = agnd, v+ = 15v, t a = 0? to +85? , typical values are at +25?, unless otherwise noted.) parameter symbol conditions min typ max units current-limit threshold (fixed) agnd - v cs _, ilim_ = v cc 40 50 60 mv agnd - v cs _, ilim_ = 0.5v 40 50 60 current-limit threshold (adjustable) agnd - v cs _, ilim_ = 1v 85 100 115 mv ilim_ adjustment range v ilim _ 0.3 2.5 v negative current-limit threshold (fixed) v cs _ - agnd, ilim_ = v cc , t a = +25 o c -75 -60 -45 mv thermal-shutdown threshold hysteresis = 15 o c +160 o c v cc undervoltage-lockout threshold rising edge, hysteresis = 20mv, pwms disabled below this level 4.05 4.40 v max8743eei 1.5 5 ? dh gate-driver on-resistance bst - lx forced to 5v (note 4) MAX8743ETX 1.5 6 ? max8743eei 1.5 5 ? dl gate-driver on-resistance dl, high state (note 4) MAX8743ETX 1.5 6 ? max8743eei 0.5 1.7 ? dl gate-driver on-resistance dl, low state (note 4) MAX8743ETX 0.5 2.7 ? dh_ gate-driver source/sink current v dh _ = 2.5v, v bst _ = v lx _ = 5v 1 a dl_ gate-driver sink current v dl _ = 2.5v 3 a dl_ gate-driver source current v dl _ = 2.5v 1 a on_, skip 2.4 logic input high voltage v ih uvp v cc - 0.4 v on_, skip 0.8 logic input low voltage v il uvp 0.05 v v cc level v cc - 0.4 float level 3.15 3.85 ref level 1.65 2.35 ton input logic level agnd level 0.5 v logic input current ton (agnd or v cc )-3+3a logic input current on_, skip , uvp -1 +1 ? pgood trip threshold (lower) with respect to error-comparator trip threshold, falling edge -12.5 -10 -7.5 % pgood trip threshold (upper) with respect to error-comparator trip threshold, rising edge +7.5 +10 +12.5 % pgood propagation delay falling edge, fb_ forced 2% below pgood trip threshold 1.5 ? pgood output low voltage i sink = 1ma 0.4 v pgood leakage current high state, forced to 5.5v 1 a
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown _______________________________________________________________________________________ 5 electrical characteristics (circuit of figure 1, v dd = v cc = 5v, skip = agnd, v+ = 15v, t a = -40? to +85? , unless otherwise noted.) (note 5) parameter symbol conditions min typ max units pwm controllers v+ battery voltage, v+ 2 28 input voltage range v cc /v dd v cc , v dd 4.5 5.5 v fb1 to agnd 1.773 1.827 fb1 to v cc 1.477 1.523 d c o utp ut v ol tag e, o u t1 v out1 v+ = 2v to 28v, skip = v cc , i load = 0 to 8a ( n ote 2) fb1 to out1 0.985 1.015 v fb2 to agnd 2.463 2.537 d c o utp ut v ol tag e, o u t2 v out2 v+ = 2v to 28v, skip = v cc , i load = 0 to 4a ( n ote 2) fb2 to out2 0.985 1.015 v output voltage adjust range out1, out2 1.0 5.5 v dual-mode threshold, low ovp, fb_ 0.05 0.15 v ovp, ilim_ v cc - 1.5 v cc - 0.4 dual-mode threshold, high fb_ 1.9 2.1 v r out1 v out1 = 1.5v 75 out_ input resistance r out2 v out2 = 2.5v 100 k ? fb_ input bias current i fb -0.1 +0.1 ? ton = agnd 120 153 ton = ref 153 195 ton = float 217 272 on-time, side 1 t on1 v+ = 24v, v out1 = 2v (note 3) ton = v cc 308 390 ns ton = agnd 160 204 ton = ref 205 263 ton = float 295 371 on-time, side 2 t on2 v+ = 24v, v out2 = 2v (note 3) ton = v cc 422 534 ns ton = agnd 125 145 ton = ref 125 145 ton = float 125 145 on-time tracking on-time 2, with respect to on-time 1 (note 3) ton = v cc 125 145 % minimum off-time t off (note 3) 500 ns quiescent supply current (v cc )i cc fb forced above the regulation point 1500 ? quiescent supply current (v dd )i dd fb forced above the regulation point 5 a quiescent supply current (v+) i+ measured at v+ 70 ? reference voltage v ref v cc = 4.5v to 5.5v, no external ref load 1.98 2.02 v reference load regulation i ref = 0 to 50? 0.01 v overvoltage trip threshold (fixed-threshold mode) ovp = gnd, with respect to fb_ regulation point, no load 112 117 % output undervoltage threshold uvp = v cc , with respect to fb_ regulation point, no load 65 75 % current-limit threshold (fixed) agnd - v cs _, ilim_ = v cc 35 65 mv
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 6 _______________________________________________________________________________________ 0 0.01 10 1 0.1 300 350 400 200 250 100 150 50 max8743 toc01 load current (a) frequency (khz) frequency vs. load current out1, skip = v cc out2, skip = v cc out1, skip = gnd out2, skip = gnd 0 50 100 150 200 250 300 350 400 4812 16 20 24 max8743 toc02 input voltage (v) frequency (khz) frequency vs. input voltage (ton = float, skip = v cc ) out1 out2 i out1 = 8a i out2 = 4a __________________________________________typical operating characteristics (circuit of figure 1, components from table 1, v in = 15v, skip = gnd, ton = unconnected, t a = +25?, unless otherwise noted.) electrical characteristics (continued) (circuit of figure 1, v dd = v cc = 5v, skip = agnd, v+ = 15v, t a = -40? to +85? , unless otherwise noted.) (note 5) note 2: when the inductor is in continuous conduction, the output voltage will have a dc regulation level higher than the error-compara - tor threshold by 50% of the output voltage ripple. in discontinuous conduction ( skip = agnd, light load), the output voltage has a dc regulation higher than the error-comparator threshold by approximately 1.5% due to slope compensation. note 3: on-time and off-time specifications are measured from the 50% point to the 50% point at dh_ with lx_ = gnd, bst_ = 5v, and a 250pf capacitor connected from dh_ to lx_. actual in-circuit times may differ due to mosfet switching speeds. note 4: production testing limitations due to package handling require relaxed maximum on-resistance specifications for the qfn package. the max8743eei and MAX8743ETX contain the same die, and the qfn package imposes no additional resis- tance in-circuit. note 5: specifications to -40? are guaranteed by design, not production tested. parameter symbol conditions min typ max units agnd - v cs _, ilim_ = 0.5v 35 65 current-limit threshold (adjustable) agnd - v cs _, ilim_ = 1v 80 120 mv v cc undervoltage-lockout threshold rising edge, hysteresis = 20mv, pwms disabled below this level 4.05 4.40 v on_, skip 2.4 logic input high voltage v ih uvp v cc - 0.4 v on_, skip 0.8 logic input low voltage v il uvp 0.05 v ton (agnd or v cc )-3+3 logic input current on_, skip , uvp -1 +1 ?
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown _______________________________________________________________________________________ 7 0 4.5 3.0 1.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 515 10 20 25 30 max8743 toc03 input voltage v+ (v) supply current (ma) no-load supply current vs. input voltage (skip = v cc ) i cc v cc = v dd = 5v i dd i+ (25 a typ) 0 100 200 300 400 500 600 700 800 900 1000 1100 max8743 toc04 input voltage v+ (v) supply current ( a) 510152 02530 no-load supply current vs. input voltage (skip = gnd) v cc = v dd = 5v i dd (600na typ) i cc i+ 10 0.01 10 1 0.1 60 70 80 90 100 40 50 20 30 max8743 toc05 load current (a) efficiency (%) efficiency vs. load current (8a components, skip = v cc ) v+ = 7v v+ = 20v v+ = 12v out1 = 1.8v 50 0.01 10 1 0.1 75 80 85 90 95 100 65 70 55 60 max8743 toc06 load current (a) efficiency (%) efficiency vs. load current (8a components, skip = gnd) v+ = 7v v+ = 20v out1 = 1.8v v+ = 12v 10 50 30 70 90 110 130 150 170 190 210 230 250 00.51.01 .5 2.0 2.5 current-limit trip point vs. ilim voltage max8743 toc09 ilim voltage (v) current-limit trip point (mv) 10 0.01 10 1 0.1 60 70 80 90 100 40 50 20 30 max8743 toc07 load current (a) efficiency (%) efficiency vs. load current (4a components, skip = v cc ) v+ = 7v v+ = 20v v+ = 12v out2 = 2.5v 80 75 0.01 10 1 0.1 95 100 90 85 max8743 toc08 load current (a) efficiency (%) efficiency vs. load current (4a components, skip = gnd) v+ = 7v v+ = 12v v+ = 20v out2 = 2.5v 1.0 1.2 1.1 1.4 1.3 1.6 1.5 1.7 1.9 1.8 2.0 1.0 1.2 1.3 1.1 1.4 1.5 1.6 1.7 1.8 max8743 toc10 ovp voltage (v) normalized threshold (v) normalized overvoltage protection threshold vs. ovp voltage max8743 toc11 i out2 2a/div 20 s/div v out2 100mv/div load-transient response (4a components, pwm mode, v out2 = 2.5v) t ypical operating characteristics (continued) (circuit of figure 1, components from table 1, v in = 15v, skip = gnd, ton = unconnected, t a = +25?, unless otherwise noted.)
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 8 _______________________________________________________________________________________ max8743 toc13 400 s/div v out2 1v/div 2.5v 0v 0v 0v 0a on2 5v/div pgood 5v/div i lx2 1a/div startup waveform (v out2 ) r out2 = 2.5 ? max8743 toc14 400 s/div v out2 1v/div 2.5v 0v 0v 0v 0v on2 5v/div pgood 5v/div dl2 5v/div shutdown waveform (v out2 ) r out2 = 2.5 ? t ypical operating characteristics (continued) (circuit of figure 1, components from table 1, v in = 15v, skip = gnd, ton = unconnected, t a = +25?, unless otherwise noted.) pin qsop tqfn name function 13 2 out1 output voltage connection for the out1 pwm. connect directly to the junction of the external inductor and output filter capacitors. out1 senses the output voltage to determine the on-time and also serves as the feedback input in fixed-output modes. 233 fb1 feed b ack inp ut for o u t1. c onnect to g n d for 1.8v fi xed outp ut or to v c c for 1.5v fi xed outp ut, or connect to a r esi stor - d i vi d er netw or k fr om o u t1 for an ad j ustab l e outp ut b etw e en 1v and 5.5v . 33 4 ilim1 current-limit threshold adjustment for out1. the current-limit threshold at cs1 is 0.1 times the voltage at ilim1. connect a resistor-divider network from ref to set the current-limit threshold between 25mv and 250mv (with 0.25v to 2.5v at ilim). connect to v cc to assert 50mv default current-limit threshold. 435 v+ battery voltage-sense connection. connect to input power source. v+ is only used to adjust the dh_ on-time for pseudofixed-frequency operation. on-time selection control input. this four-level input pin sets the dh_ on-time to determine the operating frequency. ton frequency (out1) (khz) frequency (out2) (khz) agnd 620 460 ref 485 355 open 345 255 51ton v cc 235 170 62 skip pulse-skipping control input. connect to v cc for low-noise forced-pwm mode. connect to agnd to enable pulse-skipping operation. pin description max8743 toc12 i out1 5a/div 20 s/div v out1 100mv/div load-transient response (8a components, pwm mode, v out1 = 1.8v)
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown _______________________________________________________________________________________ 9 pin description (continued) pin qsop tqfn name function 73 pgood power-good open-drain output. pgood is low when either output voltage is more than 10% above or below the normal regulation point, and during the 1.7ms soft-start time. 84 ovp overvoltage protection threshold. an overvoltage fault occurs if the voltage on fb1 or fb2 is greater than the programmed overvoltage trip threshold. adjustment range is 1v (100%) to 1.8v (180%). connect ovp to gnd to set the default overvoltage threshold of 114% of nominal. connect to v cc to disable ovp and clear the ovp latch. 95 uvp u nd er vol tag e p r otecti on thr eshol d . an und er vol tag e faul t occur s i f the vol tag e on fb1 or fb2 i s l ess than the und er vol tag e tr i p thr eshol d ( 70% of nom i nal ) . c o nnect u v p to v c c to enab l e und er vol tag e p r ot ecti on. c onnect to gn d to d i sab l e und er vol tag e p r otecti on and cl ear the u v p l atch. 10 7 ref +2.0v reference voltage output. bypass to gnd with 0.22? (min) capacitor. can supply 50? for external loads. 11 8 on1 ou t1 on / off c ontr ol inp ut. c onnect to agn d to tur n ou t1 off. c o nnect to v c c to tur n o u t1 on. 12 11 on2 ou t2 on / off c ontr ol inp ut. c onnect to agn d to tur n ou t2 off. c o nnect to v c c to tur n o u t2 on. 13 12 ilim2 current-limit threshold adjustment for out2. the current-limit threshold at cs2 is 0.1 times the voltage at ilim2. connect a resistor-divider network from ref to set the current-limit threshold between 25mv and 250mv (with 0.25v to 2.5v at ilim). connect to v cc to assert 50mv default current-limit threshold. 14 13 fb2 feedback input for out2. connect to gnd for 2.5v fixed output, or connect to a resistor-divider network from out2 for an adjustable output between 1v and 5.5v. 15 14 out2 output voltage connection for the out2 pwm. connect directly to the junction of the external inductor and output filter capacitors. out2 senses the output voltage to determine the on-time and also serves as the feedback input in fixed-output modes. 16 15 cs2 current-sense input for out2. cs2 is the input to the current-limiting circuitry for valley current limiting. for lowest cost and highest efficiency, connect to lx2. for highest accuracy, use a sense resistor. see the current-limit circuit (ilim_) section. 17 16 lx2 external inductor connection for out2. connect to the switched side of the inductor. lx2 serves as the internal lower supply voltage rail for the dh2 high-side gate driver. 18 18 dh2 high-side gate-driver output for out2. swings from lx2 to bst2. 19 19 bst2 boost flying capacitor connection for out2. connect to an external capacitor and diode according to the standard application circuit in figure 1. see the mosfet gate drivers (dh_, dl_) section. 20 20 dl2 low-side gate-driver output for out2. dl2 swings from pgnd to v dd . 21 21 v dd supply input for the dl gate drivers. connect to system supply voltage, +4.5v to +5.5v. bypass to pgnd with a low-esr 4.7? capacitor. 22 22 v cc analog supply input. connect to system supply voltage, +4.5v to +5.5v, with a 20 ? series resistor. bypass to agnd with a 1? capacitor. 23 gnd ground. combined analog and power ground. serves as negative input for cs_ amplifiers.
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 10 ______________________________________________________________________________________ standard application circuit the standard application circuit (figure 1) generates a 1.8v and a 2.5v rail for general-purpose use in note- book computers. see table 1 for component selections. table 2 lists component manufacturers. detailed description the max8743 buck controller is designed for low-volt- age power supplies for notebook computers. maxim? proprietary quick-pwm pulse-width modulator in the max8743 (figure 2) is specifically designed for han- dling fast load steps while maintaining a relatively con- stant operating frequency and inductor operating point over a wide range of input voltages. the quick-pwm architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode pwms while avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time pwm schemes. 5v bias supply (v cc and v dd ) the max8743 requires an external 5v bias supply in addition to the battery. typically, this 5v bias supply is the notebook? 95% efficient 5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the 5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the 5v supply can be generated with an external linear regulator such as the max1615. the power input and 5v bias inputs can be connected together if the input source is a fixed 4.5v to 5.5v sup- ply. if the 5v bias supply is powered up prior to the bat- tery supply, the enable signal (on1, on2) must be delayed until the battery voltage is present to ensure startup. the 5v bias supply must provide v cc and gate-drive power, so the maximum current drawn is: i bias = i cc + f (q g1 + q g2 ) = 5ma to 30ma (typ) where i cc is 1ma (typ), f is the switching frequency, and q g1 and q g2 are the mosfet data sheet total gate-charge specification limits at v gs = 5v. free-running, constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed- frequency, constant-on-time current-mode type with voltage feed-forward (figure 3). this architecture relies on the output filter capacitor? effective series resis- tance (esr) to act as a current-sense resistor, so the output ripple voltage provides the pwm ramp signal. the control algorithm is simple: the high-side switch on- time is determined solely by a one-shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. another one-shot sets a minimum off-time (400ns typ). the on-time one- pin qsop tqfn name function ?3 agnd analog ground. serves as negative input for cs_ amplifiers. connect backside pad to agnd. ? 4 pgnd power ground 24 26 dl1 low-side gate-driver output for out1. dl1 swings from pgnd to v dd . 25 27 bst1 boost fl yi ng c ap aci tor c onnecti on for o u t1. c onnect to an exter nal cap aci tor and d i od e accor d i ng to the stand ar d ap p l i cati on ci r cui t i n fi g ur e 1. s ee the m os fe t g ate d r i ver s ( d h _, d l_) secti on. 26 28 dh1 high-side gate-driver output for out1. swings from lx1 to bst1. 27 30 lx1 external inductor connection for out1. connect to the switched side of the inductor. lx1 serves as the internal lower supply voltage rail for the dh1 high-side gate driver. 28 31 cs1 current-sense input for out1. cs1 is the input to the current-limiting circuitry for valley current limiting. for lowest cost and highest efficiency, connect to lx1. for highest accuracy, use a sense resistor. see the current-limit circuit (ilim_) section. 6, 9, 10, 17, 25, 29, 36 n.c. no connection pin description (continued)
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown ______________________________________________________________________________________ 11 shot is triggered if the error comparator is low, the low- side switch current is below the current-limit threshold, and the minimum off-time one-shot has timed out (table 3). on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time for both controllers. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely pro- portional to the battery voltage as measured by the v+ input, and proportional to the output voltage. this algo- rithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. the benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. the on-times for side 1 are set 35% higher than the on- times for side 2. this is done to prevent audio-frequen- cy ?eating?between the two sides, which switch asyn- chronously for each side. the on-time is given by: on-time = k (v out + 0.075v) / v in where k is set by the ton pin-strap connection (table 4), and 0.075v is an approximation to accommodate for the expected drop across the low-side mosfet switch. one-shot timing error increases for the shorter on-time settings due to fixed propagation delays; it is approximately ?2.5% at higher frequencies and ?0% at lower frequencies. this translates to reduced switch- ing-frequency accuracy at higher frequencies (table 4). switching frequency increases as a function of load current due to the increasing drop across the low-side mosfet, which causes a faster inductor-current dis- charge ramp. the on-times guaranteed in the electrical characteristics tables are influenced by switching delays in the external high-side power mosfet. two external factors that influence switching-frequency accuracy are resistive drops in the two conduction v dd = 5v bias supply power-good indicator max8743eei v cc output1 1.8v, 8a v in 7v to 24v d3 cmpsh-3a ilim1 dl1 ton cs1 out1 gnd c3 3 ? 470 f c4 470 f d1 q4 q3 q1 q2 lx1 dh1 c5 0.1 f c6 0.1 f c7 0.22 f fb1 v dd uvp c8 1 f c1 3 ? 10 f c2 2 ? 10 f 11 12 8 19 18 17 20 16 15 6 14 7 22 25 26 27 24 5 10 2 23 21 9 c11 1 f l1 2.2 h l2 4.7 h 13 3 28 1 bst1 ilim2 ref on1 on2 ovp dl2 cs2 5v 100k ? out2 lx2 dh2 fb2 pgood v+ 4 bst2 skip c9 4.7 f r3 20 ? r1 5m ? output2 2.5v, 4a r2 10m ? d2 on/off controls figure 1. standard application circuit
max8743 loops (including inductor and pc board resistance) and the dead-time effect. these effects are the largest con- tributors to the change of frequency with changing load current. the dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times. it occurs only in pwm mode ( skip = high) when the inductor current reverses at light or neg- ative load currents. with reversed inductor current, the inductor? emf causes lx to go high earlier than nor- mal, extending the on-time by a period equal to the low-to-high dead time. for loads above the critical conduction point, the actual switching frequency is: where v drop 1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path; and t on is the on-time calculated by the max8743. automatic pulse-skipping switchover in skip mode ( skip = gnd), an inherent automatic switchover to pulse-frequency modulation (pfm) takes place at light loads. this switchover is effected by a comparator that truncates the low-side switch on-time at the inductor current? zero crossing. this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the bound- ary between continuous and discontinuous inductor-cur- rent operation (also known as the critical conduction point). for a 7v to 24v battery range, this threshold is rel- atively constant, with only a minor dependence on bat- tery voltage: where k is the on-time scale factor (table 4). the load- current level at which pfm/pwm crossover occurs, i load(skip) , is equal to 1/2 the peak-to-peak ripple cur- rent, which is a function of the inductor value (figure 4). i kv 2l v-v v load(skip) out_ in out_ in ? ? ? ? ? ? f vv tv v out drop on in drop = + + () 1 2 dual, high-efficiency, step-down controller with high impedance in shutdown 12 ______________________________________________________________________________________ table 1. component selection for standard applications table 2. component suppliers component side 1: 1.8v at 8a/ side 2: 2.5v at 4a input range 4.5v to 28v q1 high-side mosfet fairchild semiconductor fds6612a q2 low-side mosfet fairchild semiconductor fds6670a q3, q4 high/low-side mosfets fairchild semiconductor fds6982a d1, d2 rectifier nihon ep10qy03 d3 rectifier central semiconductor cmpsh-3a l1 inductor 2.2? panasonic etqp6f2r2sfa or sumida cdrh127-2r4 l2 inductor 4.7? sumida cdrh124-4r7mc c1 (3), c2 (2) input capacitor 10?, 25v taiyo yuden tmk432bj106km or tdk c4532x5r1e106m c3 (3), c4 output capacitor 470?, 6v kemet t510x477m006as or sanyo 6tpb330m r sense1 5m ? , ?%, 1w irc lr2512-01-r005-f or dale wsl-2512-r005f r sense2 10m ? , ?%, 0.5w irc lr2010-01-r010-f or dale wsl-2010-r010f manufacturer website central semiconductor www.centralsemi.com fairchild semiconductor www.fairchildsemi.com international rectifier www.irf.com irc www.irctt.com kemet www.kemet.com niec (nihon) www.niec.co.jp panasonic www.panasonic.com sanyo www.sanyo.com/components sumida www.sumida.com taiyo yuden www.t-yuden.com tdk www.component.tdk.com vishay/dale www.vishay.com
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown ______________________________________________________________________________________ 13 for example, in the standard application circuit with v out1 = 2.5v, v in = 15v, and k = 2.96? (table 4), switchover to pulse-skipping operation occurs at i load = 0.7a or about 1/6 full load. the crossover point occurs at an even lower value if a swinging (soft-satu- ration) inductor is used. the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input-voltage levels). dc output accuracy specifications refer to the threshold of the error comparator. when the inductor is in continu- ous conduction, the output voltage has a dc regulation higher than the trip level by 50% of the ripple. in discon- tinuous conduction ( skip = gnd, light-load), the output fb2 out 2 pwm controller (figure 3) v+ v+ 2v ref agnd* * in the max8743eei, agnd and pgnd are internally connected and called gnd. fault1 fault2 ref 20 ? v dd v cc out1 uvp ovp fb1 skip ton on1 on2 5v input dl1 v dd lx1 cs1 dh1 bst1 v dd v dd v dd v+ pwm controller (figure 3) pgnd* max8743 pgood v cc - 1v 0.5v i lim1 i lim2 dl2 v dd lx2 cs2 dh2 bst2 v dd v+ v cc - 1v 0.5v 2v to 28v figure 2. functional diagram
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 14 ______________________________________________________________________________________ from out ref from zero-crossing comparator error amp ton feedback mux (see figure 9) x2 to dl driver shutdown to dh driver on-time compute ton 1-shot from ilim comparator from opposite pwm to opposite pwm toff 1-shot trig trig q q s r fault q r q s r q s timer ton v+ s r q to pgood or-gate 1.1v 0.9v 0.7v 0.1v 1.14v ovp v cc - 1v uvp fb_ out_ figure 3. pwm controller (one side only) voltage has a dc regulation higher than the trip level by approximately 1.5% due to slope compensation. forced-pwm mode ( skip = high) the low-noise, forced-pwm mode ( skip = high) dis- ables the zero-crossing comparator, which controls the low-side switch on-time. this causes the low-side gate- drive waveform to become the complement of the high- side gate-drive waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop strives to maintain a duty ratio of v out /v in . the benefit of forced-pwm mode is to keep the switching frequency fairly constant, but it comes at a cost: the no-load battery current can be 10ma to 40ma, depend- ing on the external mosfets. forced-pwm mode is most useful for reducing audio- frequency noise, improving load-transient response, providing sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation of multiple-output applications that use a flyback trans- former or coupled inductor. current-limit circuit (ilim_) the current-limit circuit employs a unique ?alley?current- sensing algorithm. if the magnitude of the current-sense signal at cs_ is above the current-limit threshold, the
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown ______________________________________________________________________________________ 15 pwm is not allowed to initiate a new cycle (figure 5). the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple cur- rent. therefore, the exact current-limit characteristic and maximum load capability are a function of the sense resistance, inductor value, and battery voltage. there is also a negative current limit that prevents excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approximately 120% of the positive current limit and therefore tracks the positive current limit when ilim is adjusted. the current-limit threshold is adjusted with an internal 5? current source and an external resistor at ilim. the current-limit threshold adjustment range is from 25mv to 250mv. in the adjustable mode, the current-limit threshold voltage is precisely 1/10 the voltage seen at ilim. the threshold defaults to 50mv when ilim is con- nected to v cc . the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the cur- rent-sense signal seen by cs_ and gnd. mount or place the ic close to the low-side mosfet and sense resistor with short, direct traces, making a kelvin sense connection to the sense resistor. in figure 1, the schottky diodes (d1 and d2) provide current paths parallel to the q2/r sense and q4/r sense current paths, respectively. accurate current sensing requires d1/d2 to be off while q2/q4 conducts. avoid large cur- rent-sense voltages that, combined with the voltage across q2/q4, would allow d1/d2 to conduct. if very large sense voltages are used, connect d1/d2 in paral- lel with q2/q4 only. mosfet gate drivers (dh_, dl_) the dh and dl drivers are optimized for driving mod- erate-size, high-side and larger, low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v batt - v out differential exists. an adaptive dead-time circuit monitors the dl output and prevents the high- side fet from turning on until dl is fully off. there must be a low-resistance, low-inductance path from the dl driver to the mosfet gate for the adaptive dead-time table 3. operating mode truth table on1 on2 sk ip dl1/dl2 mode comments gnd gnd x low/low shutdown low-power shutdown state. i cc < 1? (typ). v cc gnd v cc switching/low run (pwm), low noise, side 1 only gnd v cc v cc low/switching run (pwm), low noise, side 2 only v cc v cc v cc switching/ switching run (pwm), low noise, both sides active low-noise, fixed-frequency pwm at all load conditions. low noise, high i q . v cc gnd gnd switching/low run (pwm/pfm), skip mode, side 1 only gnd v cc gnd low/switching run (pwm/pfm), skip mode, side 2 only v cc v cc gnd switching/ switching run ( p w m /p fm ) , s ki p m od e, bo th s i d es acti ve normal operation with automatic pwm/pfm switchover for pulse skipping at light loads. best light-load efficiency. v cc v cc x low/low uv fault (either side), thermal fault, or v cc below uvlo fault latch has been set by undervoltage protection circuit, thermal shutdown, or v cc below uvlo. the max8743 remains in fault mode until v cc power is cycled below por or on1/on2 is toggled. v cc v cc xhi gh/high ov fault (either side) fault latch has been set by overvoltage protection circuit. the max8743 remains in fault mode until v cc power is cycled below the 2v (typ) por level.
circuit to work properly. otherwise, the sense circuitry in the max8743 interprets the mosfet gate as ?ff while there is actually still charge left on the gate. use very short, wide traces measuring 10 to 20 squares (50 to 100 mils wide if the mosfet is 1in from the max8743). the dead time at the other edge (dh turning off) is determined by a fixed 35ns (typ) internal delay. the internal pulldown transistor that drives dl low is robust, with a 0.5 ? typical on-resistance. this helps prevent dl from being pulled up during the fast rise time of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronous- rectifier mosfet. however, for high-current applica- tions, some combinations of high- and low-side fets might be encountered that will cause excessive gate- drain coupling, which can lead to efficiency-killing, emi-producing shoot-through currents. this is often remedied by adding a resistor in series with bst, which increases the turn-on time of the high-side fet without degrading the turn-off time (figure 6). por, uvlo, and soft-start power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and prepar- ing the pwm for operation. below 4.05v (min), the v cc undervoltage-lockout (uvlo) circuitry inhibits switching by keeping dh and dl low. soft-start allows a gradual increase of the internal cur- rent-limit level during startup to reduce the input surge currents. when on1 or on2 goes high, the respective digital soft-start timer begins to ramp up the maximum allowed current limit in five steps. during the first step, the controller limits the current limit to only 20% of the full current limit. the current limit is increased by 20% every 425?. 100% current limit is available after 1.7ms ?0%. a continuously adjustable analog soft-start function can be realized by adding a capacitor in parallel with the ilim external resistor-divider network. this soft-start method requires a minimum interval between power- down and power-up to discharge the capacitor. max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 16 ______________________________________________________________________________________ bst +5v v in 5 ? dh lx max8743 figure 6. reducing the switching-node rise time figure 4. pulse-skipping/discontinuous crossover point inductor current i load = i peak / 2 on-time 0tim e i peak l v batt - v out ? i ? t = figure 5. valley current-limit threshold point inductor current i limit i load 0tim e i peak
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown ______________________________________________________________________________________ 17 power-good output (pgood) the pgood window comparator continuously monitors the output voltage for both overvoltage and undervolt- age conditions. in shutdown, standby, and soft-start, pgood is actively held low. after a digital soft-start has terminated, pgood is released when the output is within 10% of the error-comparator threshold. the pgood output is a true open-drain type with no para- sitic esd diodes. note that the pgood window detec- tor is independent of the output overvoltage and undervoltage protection (uvp) thresholds. output overvoltage protection the output voltage can be continuously monitored for overvoltage. when overvoltage protection is enabled, if the output exceeds the overvoltage threshold, overvolt- age protection is triggered and the dl low-side gate- drivers are forced high. this activates the low-side mosfet switch, which rapidly discharges the output capacitor and reduces the input voltage. note that dl latching high causes the output voltage to dip slightly negative when energy has been previously stored in the lc tank circuit. for loads that cannot tol- erate a negative voltage, place a power schottky diode across the output to act as a reverse polarity clamp. connect ovp to gnd to enable the default trip level of 114% of the nominal output. to adjust the overvoltage- protection trip level, apply a voltage from 1v (100%) to 1.8v (180%) at ovp. disable the overvoltage protection by connecting ovp to v cc . the overvoltage trip level depends on the internal or external output-voltage feedback divider and is restrict- ed by the output-voltage adjustment range (1v to 5.5v) and by the absolute maximum rating of out_. setting the overvoltage threshold higher than the output-volt- age adjustment range is not recommended. output undervoltage protection the output voltage can be continuously monitored for undervoltage. when undervoltage protection is enabled (uvp = v cc ), if the output is less than 70% of the error-amplifier trip voltage, undervoltage protection is triggered. if an undervoltage protection threshold is set, the dl low-side gate driver is forced low and the outputs float. connect uvp to gnd to disable under- voltage protection. note the nonstandard logic levels if actively driving uvp (see the electrical characteristics ). design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: 1) input voltage range. the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. lower input voltages result in better effi- ciency. 2) maximum load current. there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and filtering requirements, and thus drives output capac- itor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stress- es and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing com- ponents. 3) switching frequency. this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage due to mosfet switching losses that are proportional to frequency and v in 2 . 4) inductor operating point. this choice provides trade-offs between size vs. efficiency. low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. the minimum practical inductor value is one that causes the circuit to operate at the edge of criti- cal conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size- reduction benefit. the max8743? pulse-skipping algorithm initiates skip mode at the critical conduction point. therefore, the inductor operating point also deter- mines the load-current value at which pfm/pwm switchover occurs. the optimum point is usually found between 20% and 50% of ripple current.
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 18 ______________________________________________________________________________________ inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as follows: example: i load(max) = 8a, v in = 15v, v out = 1.8v, f = 300khz, 25% ripple current or lir = 0.25: find a low-loss inductor with the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): i peak = i load(max) + [(lir / 2) ? i load(max) ] transient response the inductor ripple current also impacts transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the amount of output sag is also a function of the maxi- mum duty factor, which can be calculated from the on- time and minimum off-time: where: where minimum off-time = 400ns typ (table 4). the amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculat- ed as: v soar = l ? i peak 2 / (2 x c out x v out ) where i peak is the peak inductor current. determining the current limit for most applications, set the max8743 current limit by the following procedure: 1) determine the minimum (valley) inductor current (il (min) ) under conditions when v in is small, v out is large, and load current is maximum. the minimum inductor current is i load minus half the ripple cur- rent (figure 4). 2) the sense resistor determines the achievable cur- rent-limit accuracy. there is a trade-off between cur- rent-limit accuracy and sense-resistor power dissipation. most applications employ a current- sense voltage of 50mv to 100mv. choose a sense resistor such that: r sense = current-limit threshold voltage / i l(min) extremely cost-sensitive applications that do not require high-accuracy current sensing can use the on- resistance of the low-side mosfet switch in place of the sense resistor by connecting cs_ to lx_ (figure 7a). use the worst-case value for r ds(on) from the mosfet data sheet, and add a margin of 0.5%/? for the rise in r ds(on) with temperature. use the calculat- ed r ds(on) and i l(min) from step 1 above to determine the current-limit threshold voltage. if the default 50mv threshold is unacceptable, set the threshold value as in step 2 above. in all cases, ensure an acceptable current limit consid- ering current-sense and resistor accuracies. duty k (v + 0.075v) v k (v + 0.075v) v + min off - time out in out out = v il c duty v v sag load max finm in out = () () () () ? - 2 2 l 1.8v (15v - 1 8v) 15v 345khz 0.25 8a 2.3 h = = . l = v(v- v) vf lir i out in out in load(max) lx dl cs max8743 lx dl cs max8743 b) a) figure 7. current-sense configurations
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown ______________________________________________________________________________________ 19 output capacitor selection the output filter capacitor must have low enough esr to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no- load condition without tripping the ovp circuit. for cpu core voltage converters and other applica- tions where the output is subject to violent load tran- sients, the output capacitor? size depends on how much esr is needed to prevent the output from dip- ping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitor? size depends on how much esr is needed to maintain an acceptable level of output voltage ripple: the actual microfarad capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and volt- age rating rather than by capacitance value (this is true of tantalums, os-cons , and other electrolytics). when using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load tran- sients. also, the capacitance must be great enough to prevent the inductor? stored energy from launching the output above the overvoltage protection threshold. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response section). output capacitor stability considerations stability is determined by the value of the esr zero rel- ative to the switching frequency. the point of instability is given by the following equation: where: for a typical 300khz application, the esr zero frequen- cy must be well below 95khz, preferably below 50khz. tantalum and os-con capacitors in widespread use at the time of publication have typical esr zero fre- quencies of 15khz. in the design example used for inductor selection, the esr needed to support 20mv p-p ripple is 20mv/2a = 10m ? . three 470?/6v kemet t510 low-esr tantalum capacitors in parallel provide 10m ? (max) esr. their typical combined esr results in a zero at 11.3khz, well within the bounds of stability. do not put high-value ceramic capacitors directly across the outputs without taking precautions to ensure stability. large ceramic capacitors can have a high- esr zero frequency and cause erratic, unstable opera- tion. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting out_ or the fb_ divider close to the inductor. unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback- loop instability. f rc esr esr f = 1 2 f f esr sw r v lir i esr pp load max ? () r v i esr dip load max () os-con is a registered trademark of sanyo electric co., ltd. ton setting side 1 frequency (khz) side 1 k-factor (s) side 2 frequency (khz) side 2 k-factor (s) approximate k-factor error (%) v cc 235 4.24 170 5.81 ?0 float 345 2.96 255 4.03 ?0 ref 485 2.08 355 2.81 ?2.5 agnd 620 1.63 460 2.18 ?2.5 table 4. frequency selection guidelines
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 20 ______________________________________________________________________________________ double-pulsing occurs due to noise on the output or because the esr is so low that there is not enough volt- age ramp in the output voltage signal. this ?ools?the error comparator into triggering a new cycle immedi- ately after the 400ns minimum off-time period has expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it may indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillations at the output after line or load perturbations that can trip the overvolt- age protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for checking stability is to apply a very fast zero-to-max load transient (refer to the max8743 ev kit manual) and carefully observe the out- put-voltage-ripple envelope for overshoot and ringing. it helps to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under- or overshoot. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. nontantalum chemistries (ceramic, aluminum, or os- con) are preferred due to their resistance to power-up surge currents: power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (>5a) when using high-voltage (>20v) ac adapters. low-current applications usually require less attention. for maximum efficiency, choose a high-side mosfet (q1) that has conduction losses equal to the switching losses at the optimum battery voltage (15v). ensure that the conduction losses at the minimum input volt- age do not exceed the package thermal limits or violate the overall thermal budget. ensure that conduction losses plus switching losses at the maximum input voltage do not exceed the package ratings or violate the overall thermal budget. choose a low-side mosfet (q2) that has the lowest possible r ds(on) , comes in a moderate to small pack- age (i.e., so-8), and is reasonably priced. ensure that the max8743 dl gate driver can drive q2; in other words, check that the gate is not pulled up by the high- side switch turning on due to parasitic drain-to-gate capacitance, causing cross-conduction problems. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the buck topology. mosfet power dissipation worst-case conduction losses occur at the duty cycle extremes. for the high-side mosfet, the worst-case- power dissipation (pd) due to resistance occurs at min- imum battery voltage: generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissipation limits often limits how small the mosfet can be. again, the optimum occurs when the switching (ac) losses equal the conduction (r ds(on) ) losses. high-side switching losses do not usually become an issue until the input is greater than approxi- mately 15v. switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the cv 2 f switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , reconsider the choice of mosfet. calculating the power dissipation in q1 due to switch- ing losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn- off times. these factors include the internal gate resis- tance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for bench eval- uation, preferably including a verification using a ther- mocouple mounted on q1: where c rss is the reverse transfer capacitance of q1, and i gate is the peak gate-drive source/sink current (1a typ). for the low-side mosfet, q2, the worst-case power dissipation always occurs at maximum battery voltage: pd(q2) 1 - v v i r out in max load 2 ds on = ? ? ? ? ? ? ? ? () () pd(q1 switching) cv fi i rss in(max) 2 load gate = pd(q1 resistance) v v i r out in min load 2 ds on = ? ? ? ? ? ? ? ? () () i i vv-v v rms load out in out in = () ? ? ? ? ? ? ? ?
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown ______________________________________________________________________________________ 21 the absolute worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not high enough to exceed the cur- rent limit. to protect against this possibility, ?verde- sign?the circuit to tolerate: i load = i limit(high) + (lir / 2) ? i load(max) where i limit(high) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. if short-circuit protection without overload protection is adequate, enable overvoltage protection, and use i load(max) to calculate component stresses. choose a schottky diode (d1) having a forward voltage low enough to prevent the q2 mosfet body diode from turning on during the dead time. as a general rule, a diode having a dc current rating equal to 1/3 of the load current is sufficient. this diode is optional and can be removed if efficiency is not critical. applications information dropout performance the output voltage adjust range for continuous-conduc- tion operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot. for best dropout per- formance, use the slower on-time settings. when work- ing with low input voltages, the duty-cycle limit must be calculated using the worst-case values for on- and off- times. manufacturing tolerances and internal propaga- tion delays introduce an error to the ton k-factor. this error is greater at higher frequencies (table 4). also, keep in mind that transient-response performance of buck regulators operating close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h = ? i up / ? i down is an indicator of ability to slew the inductor current higher in response to increased load and must always be greater than 1. as h ap- proaches 1, the absolute minimum dropout point, the inductor current is less able to increase during each switching cycle, and v sag greatly increases unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but this may be adjusted up or down to allow trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, calculate the minimum operating voltage as follows: v in(min) = [(v out + v drop1 ) / {1 - (t off(min) ? h / k)}] + v drop2 - v drop1 where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths (see the on- time one-shot (ton ) section), t off(min) is from the electrical characteristics , and k is taken from table 4. the absolute minimum input voltage is calculated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, reduce the operating frequency or add output capacitance to obtain an acceptable v sag . if operation near dropout is anticipated, calcu- late v sag to ensure adequate transient response. dropout design example: v out = 1.8v f sw = 600khz k = 1.63?, worst-case k = 1.4175? t off(min) = 500ns v drop1 = v drop2 = 100mv h = 1.5 v in(min) = (1.8v + 0.1v) / [1 - (0.5? ? 1.5) / 1.4175?] + 0.1v - 0.1v = 3.8v calculating again with h = 1 gives an absolute limit of dropout: v in(min) = (1.8v + 0.1v) / [1 - (0.5? ? 1) / 1.4175?] + 0.1v - 0.1v = 2.8v therefore, v in must be greater than 2.8v, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.8v. fixed output voltages the max8743? dual-mode operation allows the selec- tion of common voltages without requiring external components (figure 8). connect fb1 to gnd for a fixed 1.8v output or to v cc for a 1.5v output, or connect fb1 directly to out1 for a fixed 1v output. connect fb2 to gnd for a fixed 2.5v output or to out2 for a fixed 1v output.
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 22 ______________________________________________________________________________________ setting v out _ with a resistor-divider the output voltage can be adjusted from 1v to 5.5v with a resistor-divider network (figure 9). the equation for adjusting the output voltage is: where v fb _ is 1.0v and r2 is approximately 10k ? . pc board layout guidelines careful pc board layout is critical to achieve low switch- ing losses and clean, stable operation. this is especial- ly true for dual converters, where one channel can affect the other. the switching power stages require particular attention (figure 10). refer to the max1845 evaluation kit data sheet for a specific layout example. use a four-layer board. use the top side for power com- ponents and the bottom side for the ic and the sensitive ground components. use the two middle layers as ground planes, with interconnections between the top and bottom layers as needed. if possible, mount all of the power components on the top side of the board, with connecting terminals flush against one another. keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. short power traces and load con- nections are essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mil- liohm of excess trace resistance causes a measurable efficiency penalty. v v1 r1 r2 out_ fb_ =+ ? ? ? ? ? ? dl_ gnd out_ cs_ dh_ fb_ v batt v out r1 r2 max8743 figure 9. setting v out with a resistor-divider agnd plane agnd plane pgnd plane via to out1 via to pgnd plane and ic gnd via to cs1 notch v in use agnd plane to: - bypass v cc and ref - terminate external fb, ilim, ovp dividers, if used - pin-strap control inputs use pgnd plane to: - bypass v dd - connect ic ground to top-side star ground via to top-side ground top-side ground plane l2 l1 c1 c2 q1 q2 q3 q4 c in c in c in d2 d1 figure 10. pc board layout example max8743 to error amp1 to error amp2 out2 fb2 0.1v 2v 0.1v fb1 fixed 2.5v fixed 1.5v fixed 1.8v out1 figure 8. feedback mux
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown ______________________________________________________________________________________ 23 place the current-sense resistors close to the top-side star-ground point (where the ic ground connects to the top-side ground plane) to minimize current-sensing errors. avoid additional current-sensing errors by using a kelvin connection from cs_ pins to the sense resistors. the following guidelines are in order of importance: keep the space between the ground connection of the current-sense resistors short and near the via to the ic ground pin. minimize the resistance on the low-side path. the low-side path starts at the ground of the low-side fet, goes through the low-side fet, through the inductor, through the output capacitor, and returns to the ground of the low-side fet. minimize the resis- tance by keeping the components close together and the traces short and wide. minimize the resistance in the high-side path. this path starts at v in , goes through the high-side fet, through the inductor, through the input capacitor, and back to the input. when trade-offs in trace lengths must be made, it? preferable to allow the inductor charging path to be made longer than the discharge path. for example, it? better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (ref, ilim_, fb_). layout procedure 1) place the power components first, with ground termi- nals adjacent (sense resistor, c in -, c out -, d1 anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the synchronous- rectifier mosfets, preferably on the back side to keep cs_, gnd, and the dl_ gate-drive line short and wide. the dl_ gate trace must be short and wide, measur- ing 10 squares to 20 squares (50mils to 100mils wide if the mosfet is 1in from the controller ic). 3) group the gate-drive components (bst_ diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as follows: create a small analog ground plane (agnd) near the ic. connect this plane directly to gnd under the ic, and use this plane for the ground con- nection for the ref and v cc bypass capacitors, fb_, ovp, and ilim_ dividers (if any). do not con- nect the agnd plane to any ground other than the gnd pin. create another small ground island (pgnd), and use it for the v dd bypass capacitor, placed very close to the ic. connect the pgnd plane directly to gnd from the outside of the ic. 5) on the board? top side (power planes), make a star ground to minimize crosstalk between the two sides. the top-side star ground is a star connection of the input capacitors, side 1 low-side mosfet, and side 2 low-side mosfet. keep the resistance low between the star ground and the source of the low- side mosfets for accurate current limit. connect the top-side star ground (used for mosfet, input, and output capacitors) to the small pgnd island with a short, wide connection (preferably just a via). minimize crosstalk between side 1 and side 2 by directing their switching ground currents into the star ground with a notch as shown in figure 10. if multi- ple layers are available (highly recommended), cre- ate pgnd1 and pgnd2 islands on the layer just below the top-side layer (refer to the max1845 ev kit for an example) to act as an emi shield. connect each of these individually to the star-ground via, which connects the top side to the pgnd plane. add one more solid ground plane under the ic to act as an additional shield, and also connect that to the star-ground via. 6) connect the output power planes directly to the out- put filter-capacitor positive and negative terminals with multiple vias.
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 24 ______________________________________________________________________________________ pin configurations 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 cs1 lx1 dh1 bst1 dl1 gnd out2 v cc v dd dl2 bst2 dh2 lx2 cs2 fb2 ilim2 on2 on1 ref uvp ovp pgood skip ton v+ ilim1 fb1 out1 qsop top view max8743eei bst1 dl1 pgnd agnd dl2 bst2 v cc v dd n.c. pgood ovp uvp ref on1 n.c. ton 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 out2 cs2 lx2 dh2 fb2 ilim2 on2 n.c. v+ ilim1 fb1 out1 cs1 lx1 n.c. dh1 n.c. thin qfn MAX8743ETX n.c. n.c. skip chip information transistor count: 4795 process: bicmos
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown ______________________________________________________________________________________ 25 qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch note: the max8743eei does not have a heat slug. pa cka ge information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max8743 dual, high-efficiency, step-down controller with high impedance in shutdown 26 ______________________________________________________________________________________ qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l e 1 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm l1 l e package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
dual, high-efficiency, step-down controller with high impedance in shutdown max8743 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 27 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220, except for 0.4mm lead pitch package t4866-1. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. e 2 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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